Although the Intel® platform for communications infrastructure allows for superb scalability to perform deep packet inspection and encryption at a variety of throughput rates, it is capable of much more. The Intel architecture platform consists of Intel Xeon processors with up to 16 cores, 8 memory controllers, and 80 channels of PCIe Gen 3.0, which connect to Intel Communications chipsets containing communications hardware accelerators. The accelerators perform all of the encryption and data compression functions, freeing the CPUs to process applications and perform deep packet inspection.

To allow developers to take full advantage of the capabilities of the new platform and the scalability of its processors, memory, chipsets, and accelerators for deep packet inspection and other applications, Intel has created the Intel® Data Plane Development Kit (Intel DPDK), a package designed to assist in migrating packet processing applications from NPUs to the Intel Architecture platform. The DPDK maximizes application throughput and minimizes development time because it consists of optimized libraries and programming primitives that can be packaged with a virtual machine, allowing developers to easily scale by creating instances of multiple virtual machines.

To illustrate this capability, take the case of a single control plane processor and multiple virtual data plane processors distributed across two quad-core processors. Seven of the cores may be running Intel DPDK instances devoted to data plane tasks, including deep packet inspection, routing, packet forwarding, and others. Four cores may be controlling Ethernet ports, and another port is left for running in Linux user space for control plane and higher level functions. Intel QuickPath Interconnects are used to tie the CPUs together for high-speed data transfer.

The Intel DPDK package has been created to be compatible with any Intel Architecture platform, which means OEM and Independent Software Vendors can select the class of CPU that best fits their needs for performance and pricing, and develop software without concern for the processor’s performance level. It also means that, as advances are made in the performance of new processors, and core counts increase, designers will be able to quickly take advantage of them to get their deep packet inspection and telecom appliances to the marketplace.

Excerpted from the whitepaper entitled “Accelerating Deep Packet Inspection with Latest Intel® Server Technologies.”