Key Attributes of Sandy Bridge
Overall, Sandy Bridge is designed to provide 60% more performance while using 30% less energy than any previous microprocessor. In the Xeon E5 version of the CPU, there are up to eight cores available, with each core running up to 16 threads per socket, and a Last-Level Cache (LLC) of 20 MB. A maximum of four memory channels are available, with 3 R/LR-DIMMs or 2 UDIMMs per channel. Top memory speed is 1 DPC up to 1600 MHz at 1.5V. The processor contains as many as 40 PCIe lanes on 10 controllers, with sustained PCI speeds of 5 GT/s on Gen 2 CPUs. In summary, the Sandy Bridge / Xeon CPU is a powerhouse.
PCIe 3.0 Built In
Sandy Bridge CPUs have embedded PCIe 3.0. By integrating this into the architecture, Xeon E5 CPUs are capable of handling twice the throughput of units using PCIe 2.0, an important consideration when using RAID controllers or for applications that would benefit from a 10 GB/s to 40 GB/s speed increase across Ethernet.
More memory bandwidth is available in Sandy Bridge up to 1600 MHz with the Xeon E5. With four memory channels available on the E5-2600 per CPU, dual processor servers that utilize this CPU have eight independent DDR3 memory channels available.
Sandy Bridge CPUs are designed with “Turbo Mode Version 2.” This is a processor control program that tracks the utilization rate of the cores within the CPU and allows certain cores to over-clock if there is thermal headroom available or if some of the cores are being underutilized. When cores are not being fully used, either because some cores are dormant or because a particular application does not thread well, the BIOS will force the active cores to run faster. This is done by removing power from the idle cores and applying it to the active ones. This allows active applications to run faster, and new tasks to start faster.
In Part 3 of this series, we’ll look the code optimization, the instruction set, and the Xeon CPU hierarchy.
Visit the NEI website at www.nei.com or contact them directly at (877) 638-3262 to learn more about Sandy Bridge microarchitecture.