Transitioning to Sandy Bridge – Intel’s New Microarchitecture, Part 3
Mar 16, 2012
In this final segment of our three-part series on the benefits of transitioning to Intel’s Sandy Bridgeprocessors, we’ll look at the new instructions set, the model hierarchy of the E3 and E5 Xeon processor class, and the steps taken by Intel to maximize the performance of the CPU. As you will recall, Part 1 included a discussion of the applications that are likely to get the biggest benefit from transitioning to Sandy Bridge, including those that rely on real-time high-volume data transmission such as multimedia and security software, plus those that could benefit from increased data transfer rates up to 40 GB/s. Part 2 discussed the specific features of the Sandy Bridge / Xeon system, including increased memory bandwidth, embedded PCIe 3.0, and Turbo Mode. Part 3 will cement the idea that software designers and system architects responsible for maximizing data throughput should quickly move to Sandy Bridge microarchitecture.
The Sandy Bridge Instruction Set
New extensions to the x86 microprocessor instruction set are done via Advanced Encryption Standard – New Instructions (AES-NI) to boost AES-based handling of encryption and decryption. The performance of AES can be accelerated by up to 10 times over software-only execution using AES-NI. The new extension set to SSE is called Intel AVX, which is a 256-bit instruction set designed for floating-point-intensive applications. Intel AVX features enhanced performance with enriched functionality, new syntax, and wider vectors. Data management for CPU-intensive applications is enhanced as a result.
Throughout 2012, several models of the Xeon CPU will be released, including the E5-1200, -2400, -2600, and -4600. With these models, the first number after the E5 represents the number of CPUs within the platform, so the 1200 has one CPU and is the lowest cost unit produced, while the 4600 has four cores, and is designed for optimal cost and density. For most software designers, the likely choices will be the E5-2400 or E5-2600 models. While both feature two cores, the E5-2400 is optimized for density and cost, while the E5-2600 is optimized for performance, and has the largest memory in the two-core hierarchy. The E5-2600 has two QuickPack Interconnects, 80 PCIe lanes, and 24 DIMMs of memory space, compared to 1 QPI, 48 PCIe lanes, and 12 DIMMs of memory for the E5-2400. If the architecture design requires several PCIe cards in an application, the E5-2600 is by far the better choice.
Optimizing the Code
In order to maximize the benefits of Sandy Bridge microarchitecture, developers must use the best available math kernel libraries, performance primitives, profiler tools, DSP libraries, and compiler. For users of Windows and Linux operating systems, programming tools like C++, VTune Amplifier XE, Composer XE, and Parallel Inspector are all excellent choices. Thread Building Blocks (TBB), the Math Kernel Library (MKL), and Integrated Performance Primitives (IPP) can all help maximize the platform. They are available for download and testing.
The NEI team is ready to assist in your transition plans to Intel Sandy Bridge Microarchitecture and Intel Xeon Processor E5-2600 family for high-performance computing, communications platforms and security appliances. NEI offers the earliest access to test and evaluation platforms, extensive experience and field engineering expertise, ecosystem knowledge and a platform agnostic approach to designing the best deployment platform for your application. Visit the NEI website at www.nei.com/sandybridge, or contact them directly at (877) 638-3262 to learn more about Sandy Bridge microarchitecture.